1. The Field of the Invention
This invention relates to integrated circuit structures. More particularly, the present invention relates to capacitive structures used with dynamic random access memory cells formed on integrated circuits.
2. The Background Art
The miniaturization of electrical components and their integration on a single piece of semiconductor material has been the catalyst of a world-wide information revolution. As integrated circuit technology has progressed, it has been possible to store ever increasing amounts of digital data in a smaller space at less expense and still access the data randomly, quickly, and reliably. Central to this greatly increased ability to store and retrieve data has been the dynamic random access memory, or DRAM, fabricated as an integrated circuit.
In the case of mass produced DRAMs, the cost per bit of memory decreases as the number of bits which can be reliably stored on each integrated circuit increases. Thus, it is advantageous to pack as many memory cells as practically possible on each square unit of planar area available on an integrated circuit.
The memory cells of DRAMs are comprised of two main components: a transistor and a capacitor. The capacitor of each memory cell functions to store an electrical charge representing a digital value (e.g., a charged capacitor representing a 1 and a discharged capacitor representing a 0) with the transistor acting as a switch to connect the capacitor to the "outside world" via decoding and other circuitry.
The state of the art has progressed to where the transistor can be made much smaller than the capacitor. In order to function properly the capacitor must possess a minimum amount of capacitance. Generally, it is desirable that each memory cell capacitor, often generally referred to as a "memory cell," possess at least 20.times.10.sup.-15 farads, and preferably more, of charge storage capacity. If a capacitor exhibits too little capacitance, it will loose any charge placed upon it too rapidly causing errors in data storage.
The capacitive value of a capacitor is dependent upon the dielectric constant of the material placed between the plates of the capacitor, the distance between the plates, and the effective area of the plates. In the case of integrated circuits, the material used as a dielectric between the plates is generally limited to only a few materials. Also, the minimum distance between the capacitor plates is generally limited to a particular value; once that value is exceeded, the occurrence of defects becomes unacceptably high. Thus, the one parameter which can be varied to obtain an increased storage capacity is the area of the plates.
Thus, it is a goal of DRAM designers to increase the area of the capacitor plates as much as possible. Concurrently, it is also a goal to reduce the planar area occupied by the capacitor to a minimum so that as many memory cells as possible can be packed onto a single integrated circuit. Thus, various three dimensional structures have been proposed and adopted in the art to maintain the capacitive value of the capacitor at a desirably high level while keeping the planar area devoted to the capacitor at a minimum.
Among the proposed schemes for maintaining cell capacitance while decreasing the planar area devoted to the cell is a fin-like structure. See T. Ema, et. al., "3-dimensional Stacked Capacitor Cell for 16M and 64M DRAMS," Int'l. Electron Devices Meeting Tech. Digest 592-595 (1988). Disadvantageously, the process proposed in the Ema paper is not easy to scale down since the polysilicon node contact formation has to be aligned very precisely between two adjacent word lines and also between two adjacent bit or digit lines. Further, the process described in the Ema paper requires that the storage node precisely overlap the storage node contact. All these alignment tolerances will significantly increase the cell size for a given photolithography tool capacity. The structure described in the Ema paper presents multiple fabrication difficulties in view of present state of the art techniques available to maintain alignment of integrated circuit structures.
Other proposed schemes for maintaining or increasing cell capacitance in a decreasing planar area use a spread stacked capacitor. See S. Inoue, et.al., "A Spread Stacked Capacitor (SSC) Cell for 64MBit DRAMs," Int'l. Electron Devices Meeting Tech. Digest 31-34 (1989). Disadvantageously, the process described in the Inoue paper is particularly complicated and requires at least two additional mask steps to form the structures and cannot be made with self aligning contacts thereby increasing the cell size for a given photolithography tool capability.
In view of the foregoing, it would be an advance in the art to provide a structure and method for forming an integrated circuit capacitor structure which provides increased capacitance without unduly adding processing steps to the fabrication of the integrated circuit and which includes self aligning structures. It would be another advance in the art to provide a structure and method for forming an integrated circuit capacitor structure which provides a higher capacitance per square unit of planar area and which can be reliably manufactured and operated and which is particularly adapted for integration into DRAM memory cells.